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Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability
January/February 2008 (vol. 28 no. 1)
pp. 60-68
With continued technology scaling, process variations will be especially detrimental to six-transistor static memory structures (6T SRAMs). A memory architecture using three-transistor, one-diode DRAM (3T1D) cells in the L1 data cache tolerates wide process variations with little performance degradation, making it a promising choice for on-chip cache structures for next-generation microprocessors.
1. 60 W.K. Luk et al., "A 3-Transistor DRAM Cell with Gated Diode for Enhanced Speed and Retention Time," Proc. Symp. VLSI Circuits, IEEE Press, 2006, pp. 184-185.2. A. Agarwal et al., "A Process-Tolerant Cache Architecture for Improved Yield in Nanoscale Technologies," IEEE Trans. Very Large Scale Integration (VLSI) Systems, vol. 13, no. 1, Jan. 2005, pp. 27-38.3. S. Ozdemir et al., "Yield-Aware Cache Architectures," Proc. 39th Ann. IEEE/ACM Int'l Symp. Microarchitecture (MICRO 06), IEEE CS Press, 2006, pp. 15-25.4. D.A. Wood, M.D. Hill, and R.E. Kessler, "A Model for Estimating Trace-Sample Miss Ratios," Proc. ACM Sigmetrics Conf. Measurement and Modeling of Computer Systems, ACM Press, 1991, pp. 79-89.5. A.J. Bhavnagarwala, X. Tang, and J.D. Meindl, "The Impact of Intrinsic Device Fluctuations on CMOS SRAM Cell Stability," IEEE J. Solid-State Circuits, vol. 36, no. 4, Apr. 2001, pp. 658-665.
Index Terms:
variability, process variation, caches, dynamic memory
Citation:
Xiaoyao Liang, Ramon Canal, Gu-Yeon Wei, David Brooks, "Replacing 6T SRAMs with 3T1D DRAMs in the L1 Data Cache to Combat Process Variability," IEEE Micro, vol. 28, no. 1, pp. 60-68, Jan./Feb. 2008, doi:10.1109/MM.2008.12
