Low-Power, High-Performance Architecture of the PWRficient Processor Family March/April 2007 (vol. 27 no. 2) pp. 69-78
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2007.37
The dual-core PA6T-1682M system on chip (SoC) is the first design in the PWRficient family of high-performance, low-power processor designs that target server-class performance with low power consumption. The heart of the PA6T-1682M is the PA6T core, which implements the 64-bit IBM Power Architecture. The SoC implements extensive features that support embedded and mobile low-power applications.
Index Terms:
low power, high-performance, processor, computer architecture, chip multiprocessor, coherent memory system
Citation:
Tse-Yu Yeh, "Low-Power, High-Performance Architecture of the PWRficient Processor Family," IEEE Micro, vol. 27, no. 2, pp. 69-78, Mar./Apr. 2007, doi:10.1109/MM.2007.37 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb