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A Hardware Memory Race Recorder for Deterministic Replay
January/February 2007 (vol. 27 no. 1)
pp. 48-55
ASCII Text
x 
 
Min Xu, Rastislav Bod?, Mark D. Hill, "A Hardware Memory Race Recorder for Deterministic Replay," IEEE Micro, vol. 27, no. 1, pp. 48-55, January/February, 2007.
 
 
BibTex
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@article{ 10.1109/MM.2007.2,
author = {Min Xu and Rastislav Bod? and Mark D. Hill},
title = {A Hardware Memory Race Recorder for Deterministic Replay},
journal ={IEEE Micro},
volume = {27},
number = {1},
issn = {0272-1732},
year = {2007},
pages = {48-55},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2007.2},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - A Hardware Memory Race Recorder for Deterministic Replay
IS - 1
SN - 0272-1732
SP48
EP55
EPD - 48-55
A1 - Min Xu,
A1 - Rastislav Bod?,
A1 - Mark D. Hill,
PY - 2007
KW - multicore
KW - multithreading
KW - determinism
KW - shared-memory race recording
KW - cache coherence
VL - 27
JA - IEEE Micro
ER -
 
Min Xu, VMware
Rastislav Bod?, University of California, Berkeley
Mark D. Hill, University of Wisconsin at Madison
The Flight Data Recorder continually logs memory races in a multithreaded execution, enabling the deterministic replay invaluable for debugging concurrency errors, yet adds only modest hardware to a multicore chip. In experiments, recording incurred less than 2 percent runtime overhead.
Index Terms:
multicore, multithreading, determinism, shared-memory race recording, cache coherence
Citation:
Min Xu, Rastislav Bod?, Mark D. Hill, "A Hardware Memory Race Recorder for Deterministic Replay," IEEE Micro, vol. 27, no. 1, pp. 48-55, Jan./Feb. 2007, doi:10.1109/MM.2007.2
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