NoSQ: Store-Load Communication without a Store Queue

Micro
2007
Issue No. 1 - January/February
Abstract - NoSQ: Store-Load Communication without a Store Queue

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January/February 2007 (vol. 27 no. 1)

pp. 106-113

	ASCII Text	x
	Tingting Sha, Milo M.K. Martin, Amir Roth, "NoSQ: Store-Load Communication without a Store Queue," IEEE Micro, vol. 27, no. 1, pp. 106-113, January/February, 2007.

	BibTex	x
	@article{ 10.1109/MM.2007.17, author = {Tingting Sha and Milo M.K. Martin and Amir Roth}, title = {NoSQ: Store-Load Communication without a Store Queue}, journal ={IEEE Micro}, volume = {27}, number = {1}, issn = {0272-1732}, year = {2007}, pages = {106-113}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2007.17}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - NoSQ: Store-Load Communication without a Store Queue IS - 1 SN - 0272-1732 SP106 EP113 EPD - 106-113 A1 - Tingting Sha, A1 - Milo M.K. Martin, A1 - Amir Roth, PY - 2007 KW - pipeline processors KW - RISC KW - CISC KW - VLIW architectures KW - microarchitecture VL - 27 JA - IEEE Micro ER -

Tingting Sha, University of Pennsylvania

Milo M.K. Martin, University of Pennsylvania

Amir Roth, University of Pennsylvania

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2007.17

The NoSQ microarchitecture performs store-load communication without a store queue and without executing stores in the out-of-order engine. It uses speculative memory bypassing for all in-flight store-load communication, enabled by a 99.8 percent accurate store-load communication predictor. The result is a simple, fast, core data path containing no dedicated store-load forwarding structures.

Index Terms:

pipeline processors, RISC, CISC, VLIW architectures, microarchitecture

Citation:

Tingting Sha, Milo M.K. Martin, Amir Roth, "NoSQ: Store-Load Communication without a Store Queue," IEEE Micro, vol. 27, no. 1, pp. 106-113, Jan./Feb. 2007, doi:10.1109/MM.2007.17

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