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Reliability: Fallacy or Reality?
November/December 2007 (vol. 27 no. 6)
pp. 36-45
ASCII Text
x 
 
Antonio González, Scott Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, Joshua J. Yi, "Reliability: Fallacy or Reality?," IEEE Micro, vol. 27, no. 6, pp. 36-45, November/December, 2007.
 
 
BibTex
x
 
@article{ 10.1109/MM.2007.107,
author = {Antonio González and Scott Mahlke and Shubu Mukherjee and Resit Sendag and Derek Chiou and Joshua J. Yi},
title = {Reliability: Fallacy or Reality?},
journal ={IEEE Micro},
volume = {27},
number = {6},
issn = {0272-1732},
year = {2007},
pages = {36-45},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2007.107},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Reliability: Fallacy or Reality?
IS - 6
SN - 0272-1732
SP36
EP45
EPD - 36-45
A1 - Antonio González,
A1 - Scott Mahlke,
A1 - Shubu Mukherjee,
A1 - Resit Sendag,
A1 - Derek Chiou,
A1 - Joshua J. Yi,
PY - 2007
KW - control structure reliability
KW - testing
KW - and fault-tolerance; control structures and microprogramming; hardware; reliability
KW - testing
KW - and fault-tolerance; arithmetic and logic structures; memory structures; performance and reliability
VL - 27
JA - IEEE Micro
ER -
 
Scott Mahlke, University of Michigan
Resit Sendag, University of Rhode Island
Derek Chiou, University of Texas at Austin
Joshua J. Yi, Freescale Semiconductor
As chip architects and manufacturers plumb ever-smaller process technologies, new species of faults are compromising device reliability. Following an introduction by Antonio González, Scott Mahlke and Shubu Mukherjee debate whether reliability is a legitimate concern for the microarchitect. Topics include the costs of adding reliability versus those of ignoring it, how to measure it, techniques for improving it, and whether consumers really want it.

1. 36 S. Borkar, "Microarchitecture and Design Challenges for Gigascale Integration," keynote address, 37th Ann. IEEE/ACM Int'l Symp. Microarchitecture, 2004.2. National Software Testing Labs, http:/www.nstl.com.3. R. Mariani, G. Boschi, and A. Ricca, "A System-Level Approach for Memory Robustness," Proc. Int'l Conf. Memory Technology and Design(ICMTD 05), 2005, http://www.icmtd.comproceedings.htm.4. J. Srinivasan et al., "Lifetime Reliability: Toward an Architectural Solution," IEEE Micro, vol. 25, no. 3, May-June 2005, pp. 70-80.5. Center for Advanced Life Cycle Engineering, Univ. of Maryland; http:/www.calce.umd.edu.6. D. Ernst et al., "Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation," Proc. 36th Ann. Int'l Symp. Microarchitecture (MICRO 03), IEEE CS Press, 2003, pp. 7-18.7. S.E. Michalak et al., "Predicting the Number of Fatal Soft Errors in Los Alamos National Laboratory's ASC Q Supercomputer," IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, Sept. 2005, pp. 329-335.

Index Terms:
control structure reliability, testing, and fault-tolerance; control structures and microprogramming; hardware; reliability, testing, and fault-tolerance; arithmetic and logic structures; memory structures; performance and reliability
Citation:
Antonio González, Scott Mahlke, Shubu Mukherjee, Resit Sendag, Derek Chiou, Joshua J. Yi, "Reliability: Fallacy or Reality?," IEEE Micro, vol. 27, no. 6, pp. 36-45, Nov./Dec. 2007, doi:10.1109/MM.2007.107
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