Tolerating Cache-Miss Latency with Multipass Pipelines

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January/February 2006 (vol. 26 no. 1)

pp. 40-47

	ASCII Text	x
	Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu, "Tolerating Cache-Miss Latency with Multipass Pipelines," IEEE Micro, vol. 26, no. 1, pp. 40-47, January/February, 2006.

	BibTex	x
	@article{ 10.1109/MM.2006.25, author = {Ronald D. Barnes and Shane Ryoo and Wen-mei W. Hwu}, title = {Tolerating Cache-Miss Latency with Multipass Pipelines}, journal ={IEEE Micro}, volume = {26}, number = {1}, issn = {0272-1732}, year = {2006}, pages = {40-47}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2006.25}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Tolerating Cache-Miss Latency with Multipass Pipelines IS - 1 SN - 0272-1732 SP40 EP47 EPD - 40-47 A1 - Ronald D. Barnes, A1 - Shane Ryoo, A1 - Wen-mei W. Hwu, PY - 2006 KW - Flea-flicker KW - multipass pipelining KW - memory-latency tolerance KW - in-order design VL - 26 JA - IEEE Micro ER -

Ronald D. Barnes, George Mason University

Shane Ryoo, University of Illinois, Urbana-Champaign

Wen-mei W. Hwu, University of Illinois, Urbana-Champaign

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.25

Multipass pipelining uses compile-time scheduling to exploit parallelism and persistent advance execution to achieve memory-latency tolerance, while maintaining the simplicity of an in-order design.

Index Terms:

Flea-flicker, multipass pipelining, memory-latency tolerance, in-order design

Citation:

Ronald D. Barnes, Shane Ryoo, Wen-mei W. Hwu, "Tolerating Cache-Miss Latency with Multipass Pipelines," IEEE Micro, vol. 26, no. 1, pp. 40-47, Jan./Feb. 2006, doi:10.1109/MM.2006.25

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