Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance

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January/February 2006 (vol. 26 no. 1)

pp. 10-20

	ASCII Text	x
	Onur Mutlu, Hyesoon Kim, Yale N. Patt, "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance," IEEE Micro, vol. 26, no. 1, pp. 10-20, January/February, 2006.

	BibTex	x
	@article{ 10.1109/MM.2006.10, author = {Onur Mutlu and Hyesoon Kim and Yale N. Patt}, title = {Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance}, journal ={IEEE Micro}, volume = {26}, number = {1}, issn = {0272-1732}, year = {2006}, pages = {10-20}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2006.10}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance IS - 1 SN - 0272-1732 SP10 EP20 EPD - 10-20 A1 - Onur Mutlu, A1 - Hyesoon Kim, A1 - Yale N. Patt, PY - 2006 KW - Runahead execution KW - memory latency tolerance KW - processors VL - 26 JA - IEEE Micro ER -

Onur Mutlu, University of Texas at Austin

Hyesoon Kim, University of Texas at Austin

Yale N. Patt, University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.10

Several simple techniques can make runahead execution more efficient by reducing the number of instructions executed and thereby reducing the additional energy consumption typically associated with runahead execution.

Index Terms:

Runahead execution, memory latency tolerance, processors

Citation:

Onur Mutlu, Hyesoon Kim, Yale N. Patt, "Efficient Runahead Execution: Power-Efficient Memory Latency Tolerance," IEEE Micro, vol. 26, no. 1, pp. 10-20, Jan./Feb. 2006, doi:10.1109/MM.2006.10

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