Adaptive History-Based Memory Schedulers for Modern Processors

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January/February 2006 (vol. 26 no. 1)

pp. 22-29

	ASCII Text	x
	Ibrahim Hur, Calvin Lin, "Adaptive History-Based Memory Schedulers for Modern Processors," IEEE Micro, vol. 26, no. 1, pp. 22-29, January/February, 2006.

	BibTex	x
	@article{ 10.1109/MM.2006.1, author = {Ibrahim Hur and Calvin Lin}, title = {Adaptive History-Based Memory Schedulers for Modern Processors}, journal ={IEEE Micro}, volume = {26}, number = {1}, issn = {0272-1732}, year = {2006}, pages = {22-29}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2006.1}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Adaptive History-Based Memory Schedulers for Modern Processors IS - 1 SN - 0272-1732 SP22 EP29 EPD - 22-29 A1 - Ibrahim Hur, A1 - Calvin Lin, PY - 2006 KW - Memory schedulers KW - memory bandwidth KW - processors KW - DRAM KW - IBM Power5 VL - 26 JA - IEEE Micro ER -

Ibrahim Hur, IBM Corp. and The University of Texas at Austin

Calvin Lin, The University of Texas at Austin

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2006.1

Careful memory scheduling can increase memory bandwidth and overall system performance. We present a new memory scheduler that makes decisions based on the history of recently scheduled operations, providing two advantages: It can better reason about the delays associated with complex DRAM structure, and it can adapt to different observed workload.

Index Terms:

Memory schedulers, memory bandwidth, processors, DRAM, IBM Power5

Citation:

Ibrahim Hur, Calvin Lin, "Adaptive History-Based Memory Schedulers for Modern Processors," IEEE Micro, vol. 26, no. 1, pp. 22-29, Jan./Feb. 2006, doi:10.1109/MM.2006.1

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