Power-Conscious Design of the Cell Processor's Synergistic Processor Element September/October 2005 (vol. 25 no. 5) pp. 10-18
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.97
The authors describe the low-power design of the synergistic processor element (SPE) of CELL processor developed by SONY, Toshiba and IBM. CMOS static gates implement most of the logic, and dynamic circuits are used in critical areas. Tight coupling of the instruction set architecture, microarchitecture, and physical implementation achieves a compact, power-efficient design.
Index Terms:
Synergistic processor element, SPE, Cell Processor, CMOS, power-conscious design, low power
Citation:
Osamu Takahashi, Scott Cottier, Sang H. Dhong, Brian Flachs, Joel Silberman, "Power-Conscious Design of the Cell Processor's Synergistic Processor Element," IEEE Micro, vol. 25, no. 5, pp. 10-18, Sep./Oct. 2005, doi:10.1109/MM.2005.97 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||