Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption July/August 2005 (vol. 25 no. 4) pp. 10-19
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.70
An effective approach to reducing processor power consumption is to adaptively activate and deactivate hardware resources. The authors propose a look-ahead scheme that adjusts the processor issue rate triggered by main-memory accesses. This architecture-independent technique is particularly effective for memory-intensive applications. Combined with an existing technique based on IPC values, it also reduces power consumption for computation-intensive applications.
Index Terms:
Low-power design, Processor Architectures
Citation:
Zhichun Zhu, Xiaodong Zhang, "Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption," IEEE Micro, vol. 25, no. 4, pp. 10-19, July/Aug. 2005, doi:10.1109/MM.2005.70 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||