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Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors
January/February 2005 (vol. 25 no. 1)
pp. 41-49
ASCII Text
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Avinash Karanth Kodi, Ahmed Louri, "Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors," IEEE Micro, vol. 25, no. 1, pp. 41-49, January/February, 2005.
 
 
BibTex
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@article{ 10.1109/MM.2005.7,
author = {Avinash Karanth Kodi and Ahmed Louri},
title = {Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors},
journal ={IEEE Micro},
volume = {25},
number = {1},
issn = {0272-1732},
year = {2005},
pages = {41-49},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.7},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors
IS - 1
SN - 0272-1732
SP41
EP49
EPD - 41-49
A1 - Avinash Karanth Kodi,
A1 - Ahmed Louri,
PY - 2005
VL - 25
JA - IEEE Micro
ER -
 
Avinash Karanth Kodi, University of Arizona
Ahmed Louri, University of Arizona
The architecture proposed here reduces remote memory access latency by increasing connectivity and maximizing channel availability for remote communication. It also provides efficient and fast unicast, multicast, and broadcast capabilities, using a combination of aggressively designed multiplexing techniques. Simulations show that this architecture provides excellent interconnect support for a highly scalable, high-bandwidth, low-latency network.
Citation:
Avinash Karanth Kodi, Ahmed Louri, "Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors," IEEE Micro, vol. 25, no. 1, pp. 41-49, Jan./Feb. 2005, doi:10.1109/MM.2005.7
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