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Kilo-Instruction Processors: Overcoming the Memory Wall
May/June 2005 (vol. 25 no. 3)
pp. 48-57
ASCII Text
x 
 
Adri? Cristal, Oliverio J. Santana, Francisco Cazorla, Marco Galluzzi, Tanaus? Ram?rez, Miquel Pericas, Mateo Valero, "Kilo-Instruction Processors: Overcoming the Memory Wall," IEEE Micro, vol. 25, no. 3, pp. 48-57, May/June, 2005.
 
 
BibTex
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@article{ 10.1109/MM.2005.53,
author = {Adri? Cristal and Oliverio J. Santana and Francisco Cazorla and Marco Galluzzi and Tanaus? Ram?rez and Miquel Pericas and Mateo Valero},
title = {Kilo-Instruction Processors: Overcoming the Memory Wall},
journal ={IEEE Micro},
volume = {25},
number = {3},
issn = {0272-1732},
year = {2005},
pages = {48-57},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.53},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Kilo-Instruction Processors: Overcoming the Memory Wall
IS - 3
SN - 0272-1732
SP48
EP57
EPD - 48-57
A1 - Adri? Cristal,
A1 - Oliverio J. Santana,
A1 - Francisco Cazorla,
A1 - Marco Galluzzi,
A1 - Tanaus? Ram?rez,
A1 - Miquel Pericas,
A1 - Mateo Valero,
PY - 2005
KW - Kilo-instruction processors
KW - superscalar processors
KW - in-flight instructions
KW - memory wall
KW - ROB
KW - issue queue
VL - 25
JA - IEEE Micro
ER -
 
Adri? Cristal, Universitat Polit?cnica de Catalunya and Barcelona Supercomputing Center
Oliverio J. Santana, Universitat Polit?cnica de Catalunya and Barcelona Supercomputing Center
Francisco Cazorla, Universitat Polit?cnica de Catalunya and Barcelona Supercomputing Center
Marco Galluzzi, Universitat Polit?cnica de Catalunya and Barcelona Supercomputing Center
Tanaus? Ram?rez, Universitat Polit?cnica de Catalunya and Barcelona Supercomputing Center
Miquel Pericas, Universitat Polit?cnica de Catalunya and Barcelona Supercomputing Center
Mateo Valero, Universitat Polit?cnica de Catalunya and Barcelona Supercomputing Center
Kilo-instruction processors are a new type of out-of-order superscalar processor that overlaps long memory access delays by maintaining thousands of in-flight instructions, in a scalable, efficient manner.
Index Terms:
Kilo-instruction processors, superscalar processors, in-flight instructions, memory wall, ROB, issue queue
Citation:
Adri? Cristal, Oliverio J. Santana, Francisco Cazorla, Marco Galluzzi, Tanaus? Ram?rez, Miquel Pericas, Mateo Valero, "Kilo-Instruction Processors: Overcoming the Memory Wall," IEEE Micro, vol. 25, no. 3, pp. 48-57, May/June 2005, doi:10.1109/MM.2005.53
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