Cell Processor Low-Power Design Methodology

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November/December 2005 (vol. 25 no. 6)

pp. 71-78

	ASCII Text	x
	Daniel Stasiak, Rajat Chaudhry, Dennis Cox, Stephen Posluszny, Jim Warnock, Steve Weitzel, Dieter Wendel, Michael Wang, "Cell Processor Low-Power Design Methodology," IEEE Micro, vol. 25, no. 6, pp. 71-78, November/December, 2005.

	BibTex	x
	@article{ 10.1109/MM.2005.107, author = {Daniel Stasiak and Rajat Chaudhry and Dennis Cox and Stephen Posluszny and Jim Warnock and Steve Weitzel and Dieter Wendel and Michael Wang}, title = {Cell Processor Low-Power Design Methodology}, journal ={IEEE Micro}, volume = {25}, number = {6}, issn = {0272-1732}, year = {2005}, pages = {71-78}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2005.107}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Cell Processor Low-Power Design Methodology IS - 6 SN - 0272-1732 SP71 EP78 EPD - 71-78 A1 - Daniel Stasiak, A1 - Rajat Chaudhry, A1 - Dennis Cox, A1 - Stephen Posluszny, A1 - Jim Warnock, A1 - Steve Weitzel, A1 - Dieter Wendel, A1 - Michael Wang, PY - 2005 KW - Cell processor KW - low power consumption KW - VLSI KW - design methodology VL - 25 JA - IEEE Micro ER -

Daniel Stasiak, STG at IBM in Austin, Texas

Rajat Chaudhry, STG at IBM in Austin, Texas

Dennis Cox, STG at IBM in Rochester, Minnesota

Stephen Posluszny, STG at IBM in Austin, Texas

Jim Warnock, STG at IBM in Yorktown Height, New York

Steve Weitzel, STG at IBM in Austin, Texas

Dieter Wendel, STG at IBM in Boeblingen, Germany

Michael Wang, STG at IBM in Austin, Texas

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2005.107

Power consumption is one of the major challenges in VLSI Design. Power constrained designs must attack power reduction with many techniques and need tools to accurately predict the power consumption to provide designers feedback on the efficiency of the power management logic. This paper presents the reduction techniques used, the methodology behind cycle accurate power estimation, and hardware measurements vs. power estimates correlation on the first generation CELL Processor.

Index Terms:

Cell processor, low power consumption, VLSI, design methodology

Citation:

Daniel Stasiak, Rajat Chaudhry, Dennis Cox, Stephen Posluszny, Jim Warnock, Steve Weitzel, Dieter Wendel, Michael Wang, "Cell Processor Low-Power Design Methodology," IEEE Micro, vol. 25, no. 6, pp. 71-78, Nov./Dec. 2005, doi:10.1109/MM.2005.107

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