Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance November/December 2004 (vol. 24 no. 6) pp. 62-73
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.71
Continual flow pipelines let a processor core sustain a very large and adaptive instruction window while keeping its scheduler and register file small. The resulting improved cache efficiency, resource decoupling, and look-ahead capability enable many such cores to reside on a single chip for high throughput while enabling high single-thread performance.
Citation:
Srikanth T. Srinivasan, Ravi Rajwar, Haitham Akkary, Amit Gandhi, Michael Upton, "Continual Flow Pipelines: Achieving Resource-Efficient Latency Tolerance," IEEE Micro, vol. 24, no. 6, pp. 62-73, Nov./Dec. 2004, doi:10.1109/MM.2004.71 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||