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Synchronous Dataflow Architecture for Network Processors
September/October 2004 (vol. 24 no. 5)
pp. 10-18
ASCII Text
x 
 
Jakob Carlstr?, Thomas Bod?, "Synchronous Dataflow Architecture for Network Processors," IEEE Micro, vol. 24, no. 5, pp. 10-18, September/October, 2004.
 
 
BibTex
x
 
@article{ 10.1109/MM.2004.57,
author = {Jakob Carlstr? and Thomas Bod?},
title = {Synchronous Dataflow Architecture for Network Processors},
journal ={IEEE Micro},
volume = {24},
number = {5},
issn = {0272-1732},
year = {2004},
pages = {10-18},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2004.57},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Synchronous Dataflow Architecture for Network Processors
IS - 5
SN - 0272-1732
SP10
EP18
EPD - 10-18
A1 - Jakob Carlstr?,
A1 - Thomas Bod?,
PY - 2004
VL - 24
JA - IEEE Micro
ER -
 
Jakob Carlstr?, Xelerated
Thomas Bod?, Xelerated
The packet instruction set computer (PISC) architecture is a synchronous dataflow architecture developed for network processors. It uses a deep pipeline that contains two types of processing elements: PISC processors, which perform programmable data manipulation, and I/O processors, which provide access to shared resources such as look-up table memory, hardware accelerators, or coprocessors.
Citation:
Jakob Carlstr?, Thomas Bod?, "Synchronous Dataflow Architecture for Network Processors," IEEE Micro, vol. 24, no. 5, pp. 10-18, Sep./Oct. 2004, doi:10.1109/MM.2004.57
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