Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2

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	Similar Articles Articles by Taeweon Suh Articles by Hsien-Hsin S. Lee Articles by Douglas M. Blough

September/October 2004 (vol. 24 no. 5)

pp. 70-78

	ASCII Text	x
	Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough, "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2," IEEE Micro, vol. 24, no. 5, pp. 70-78, September/October, 2004.

	BibTex	x
	@article{ 10.1109/MM.2004.50, author = {Taeweon Suh and Hsien-Hsin S. Lee and Douglas M. Blough}, title = {Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2}, journal ={IEEE Micro}, volume = {24}, number = {5}, issn = {0272-1732}, year = {2004}, pages = {70-78}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2004.50}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2 IS - 5 SN - 0272-1732 SP70 EP78 EPD - 70-78 A1 - Taeweon Suh, A1 - Hsien-Hsin S. Lee, A1 - Douglas M. Blough, PY - 2004 VL - 24 JA - IEEE Micro ER -

Taeweon Suh, Georgia Institute of Technology

Hsien-Hsin S. Lee, Georgia Institute of Technology

Douglas M. Blough, Georgia Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.50

Experiments with actual heterogeneous multiprocessor platforms on a shared-bus measure the effectiveness of two cache coherence techniques. This integration approach, snoop-hit buffer, and the accompanying region-based cache coherence approach yield significant speedups compared to a pure software solution.

Citation:

Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough, "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2," IEEE Micro, vol. 24, no. 5, pp. 70-78, Sep./Oct. 2004, doi:10.1109/MM.2004.50

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