Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1

Micro
2004
Issue No. 4 - July/August
Abstract - Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1

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July/August 2004 (vol. 24 no. 4)

pp. 33-41

	ASCII Text	x
	Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough, "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1," IEEE Micro, vol. 24, no. 4, pp. 33-41, July/August, 2004.

	BibTex	x
	@article{ 10.1109/MM.2004.33, author = {Taeweon Suh and Hsien-Hsin S. Lee and Douglas M. Blough}, title = {Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1}, journal ={IEEE Micro}, volume = {24}, number = {4}, issn = {0272-1732}, year = {2004}, pages = {33-41}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2004.33}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1 IS - 4 SN - 0272-1732 SP33 EP41 EPD - 33-41 A1 - Taeweon Suh, A1 - Hsien-Hsin S. Lee, A1 - Douglas M. Blough, PY - 2004 VL - 24 JA - IEEE Micro ER -

Taeweon Suh, Georgia Institute of Technology

Hsien-Hsin S. Lee, Georgia Institute of Technology

Douglas M. Blough, Georgia Institute of Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2004.33

This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution.

Citation:

Taeweon Suh, Hsien-Hsin S. Lee, Douglas M. Blough, "Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1," IEEE Micro, vol. 24, no. 4, pp. 33-41, July/Aug. 2004, doi:10.1109/MM.2004.33

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