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Design Space Exploration for Real-Time Embedded Stream Processors
July/August 2004 (vol. 24 no. 4)
pp. 54-66
ASCII Text
x 
 
Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner, "Design Space Exploration for Real-Time Embedded Stream Processors," IEEE Micro, vol. 24, no. 4, pp. 54-66, July/August, 2004.
 
 
BibTex
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@article{ 10.1109/MM.2004.25,
author = {Sridhar Rajagopal and Joseph R. Cavallaro and Scott Rixner},
title = {Design Space Exploration for Real-Time Embedded Stream Processors},
journal ={IEEE Micro},
volume = {24},
number = {4},
issn = {0272-1732},
year = {2004},
pages = {54-66},
doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2004.25},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Micro
TI - Design Space Exploration for Real-Time Embedded Stream Processors
IS - 4
SN - 0272-1732
SP54
EP66
EPD - 54-66
A1 - Sridhar Rajagopal,
A1 - Joseph R. Cavallaro,
A1 - Scott Rixner,
PY - 2004
VL - 24
JA - IEEE Micro
ER -
 
Sridhar Rajagopal, WiQuest Communications
Joseph R. Cavallaro, Rice University
Scott Rixner, Rice University
This tool explores tradeoffs between organization and number of ALUs and clock frequency in a stream processor. The tool provides candidate low-power configurations and estimates of their real-time performance. The tool relates instruction-level, subword, and data parallelism to functional units' organization and utilization. The exploration methodology is applicable to all embedded-processor designs in signal and media processing.
Citation:
Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner, "Design Space Exploration for Real-Time Embedded Stream Processors," IEEE Micro, vol. 24, no. 4, pp. 54-66, July/Aug. 2004, doi:10.1109/MM.2004.25
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