Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches
November/December 2003 (vol. 23 no. 6)
pp. 99-107
ASCII Text
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Changkyu Kim, Doug Burger, Stephen W. Keckler,
"Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches,"
IEEE Micro, vol. 23, no. 6, pp. 99-107, November/December, 2003.
BibTex
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@article{
10.1109/MM.2003.1261393, author = {Changkyu Kim and Doug Burger and Stephen W. Keckler}, title = {Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches}, journal ={IEEE Micro}, volume = {23}, number = {6}, issn = {0272-1732}, year = {2003}, pages = {99-107}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2003.1261393}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }
RefWorks Procite/RefMan/Endnote
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TY - MGZN JO - IEEE Micro TI - Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches IS - 6 SN - 0272-1732 SP99 EP107 EPD - 99-107 A1 - Changkyu Kim, A1 - Doug Burger, A1 - Stephen W. Keckler, PY - 2003 VL - 23 JA - IEEE Micro ER -
Nonuniform cache access designs solve the on-chip wire delay problem for future large integrated caches. By embedding a network in the cache, NUCA designs let data migrate within the cache, clustering the working set nearest the processor.
Citation:
Changkyu Kim, Doug Burger, Stephen W. Keckler, "Nonuniform Cache Architectures for Wire-Delay Dominated On-Chip Caches," IEEE Micro, vol. 23, no. 6, pp. 99-107, Nov./Dec. 2003, doi:10.1109/MM.2003.1261393
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