Chain: A Delay-Insensitive Chip Area Interconnect

Micro
2002
Issue No. 5 - September/October
Abstract - Chain: A Delay-Insensitive Chip Area Interconnect

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September/October 2002 (vol. 22 no. 5)

pp. 16-23

	ASCII Text	x
	John Bainbridge, Steve Furber, "Chain: A Delay-Insensitive Chip Area Interconnect," IEEE Micro, vol. 22, no. 5, pp. 16-23, September/October, 2002.

	BibTex	x
	@article{ 10.1109/MM.2002.1044296, author = {John Bainbridge and Steve Furber}, title = {Chain: A Delay-Insensitive Chip Area Interconnect}, journal ={IEEE Micro}, volume = {22}, number = {5}, issn = {0272-1732}, year = {2002}, pages = {16-23}, doi = {http://doi.ieeecomputersociety.org/10.1109/MM.2002.1044296}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Micro TI - Chain: A Delay-Insensitive Chip Area Interconnect IS - 5 SN - 0272-1732 SP16 EP23 EPD - 16-23 A1 - John Bainbridge, A1 - Steve Furber, PY - 2002 VL - 22 JA - IEEE Micro ER -

John Bainbridge

Steve Furber

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MM.2002.1044296

The increasing complexity of system-on-a-chip designs exposes the limits imposed by the standard synchronous bus. the authors propose a mixed system as a solution.

Citation:

John Bainbridge, Steve Furber, "Chain: A Delay-Insensitive Chip Area Interconnect," IEEE Micro, vol. 22, no. 5, pp. 16-23, Sep./Oct. 2002, doi:10.1109/MM.2002.1044296

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