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40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007)
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing
Chicago, Illinois, USA
December 01-December 05
ISBN: 0-7695-3047-8
Parameter variation is detrimental to a processor's frequency and leakage power. One proposed technique to mitigate it is Fine-Grain Body Biasing (FGBB), where different parts of the processor chip are given a voltage bias that changes the speed and leakage proper- ties of their transistors. This technique has been proposed for static application, with the bias voltages being programmed at manufac- turing time for worst-case conditions. In this paper, we introduce Dynamic FGBB (D-FGBB), which allows the continuous re-evaluation of the bias voltages to adapt to dynamic conditions. Our results show that D-FGBB is very versa- tile and effective. Specifically, with the processor working in nor- mal mode at fixed frequency, D-FGBB reduces the leakage power of the chip by an average of 28?42% compared to static FGBB. Alternatively, with the processor working in a high-performance mode, D-FGBB increases the processor frequency by an average of 7?9% compared to static FGBB -- or 7?16% compared to no body biasing. Finally, we also show that D-FGBB can be syner- gistically combined with Dynamic Voltage and Frequency Scaling (DVFS), creating an effective means to manage power.
Citation:
Radu Teodorescu, Jun Nakano, Abhishek Tiwari, Josep Torrellas, "Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing," micro, pp.27-42, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007), 2007
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