Technology scaling, characterized by decreasing feature size, thin- ning gate oxide, and non-ideal voltage scaling, will become a major hindrance to microprocessor reliability in future technology gener- ations. Physical analysis of device failure mechanisms has shown that most wearout mechanisms projected to plague future technol- ogy generations are progressive, meaning that the circuit-level ef- fects of wearout develop and intensify with age over the lifetime of the chip. This work leverages the progression of wearout over time in order to present a low-cost hardware structure that identi- fies increasing propagation delay, which is symptomatic of many forms of wearout, to accurately forecast the failure of microarchi- tectural structures. To motivate the use of this predictive technique, an HSPICE analysis of the effects of one particular failure mecha- nism, gate oxide breakdown, on gates from a standard cell library characterized for a 90 nm process is presented. This gate-level anal- ysis is then used to demonstrate the aggregate change in output de- lay of high-level structures within a synthesized Verilog model of an embedded microprocessor core. Leveraging this analysis, a self- calibrating hardware structure for conducting statistical analysis of output delay is presented and its efficacy in predicting the failure of a variety of structures within the microprocessor core is evaluated.