39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06) Coherence Ordering for Ring-based Chip Multiprocessors Orlando, Florida, USA December 09-December 13 ISBN: 0-7695-2732-9
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MICRO.2006.14
Ring interconnects may be an attractive solution for future chip multiprocessors because they can enable faster links than buses and simpler switches than arbitrary switched interconnects. Moreover, a ring naturally orders requests sufficiently to enable directory-less coherence, but not in the total order that buses provide for snooping coherence. Existing cache coherence protocols for rings either establish a (total) ordering point (ORDERING-POINT) or use a greedy order (GREEDY-ORDER) with unbounded retries. In this work, we propose a new class of ring protocols, RINGORDER, in which requests complete in ring position order to achieve two benefits. First, RING-ORDER improves performance relative to ORDERING-POINT by activating requests immediately instead of waiting for them to reach the ordering point. Second, it improves performance stability relative to GREEDY-ORDER by not using retries. Thus, the new RING-ORDER combines the best of ORDERING-POINT (good performance stability) with the best of GREEDY-ORDER (good average performance).
Citation:
Michael R. Marty, Mark D. Hill, "Coherence Ordering for Ring-based Chip Multiprocessors," micro, pp.309-320, 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06), 2006 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||