38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05) How to Fake 1000 Registers Barcelona, Spain November 12-November 16 ISBN: 0-7695-2440-0
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MICRO.2005.21
Large numbers of logical registers can improve performance by allowing fast access to multiple subroutine contexts (register windows) and multiple thread contexts (multithreading). Support for both of these together requires a multiplicative number of registers that quickly becomes prohibitive. We overcome this limitation with the virtual context architecture (VCA), a new register-file architecture that virtualizes logical register contexts. VCA works by treating the physical registers as a cache of a much larger memorymapped logical register space. Complete contexts, whether activation records or threads, are no longer required to reside in their entirety in the physical register file. A VCA implementation of register windows on a single-threaded machine reduces data cache accesses by 20%, providing the same performance as a conventional machine while requiring one fewer cache port. Using VCA to support multithreading enables a four-thread machine to use half as many physical registers without a significant performance loss. VCA naturally extends to support both multithreading and register windows, providing higher performance with significantly fewer registers than a conventional machine.
Citation:
David W. Oehmke, Nathan L. Binkert, Trevor Mudge, Steven K. Reinhardt, "How to Fake 1000 Registers," micro, pp.7-18, 38th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'05), 2005 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||