Keeping up with the increase in system design complexity requires the deployment of extensive engineering re-use technologies [15], so-called platform-based design techniques [8]. When creating derivatives of such a complex systems-on-chip (SOC) platform, verification represents 70% of the overall cost. In this process, functional verification has become a huge obstacle. Engineers are assumed to know how to ensure conformance to an ambiguous specification by developing a million test vectors, which may represent only 50 milliseconds of real-time operation underlines Bob Payne, CTO Philips Semiconductors US [26]. Moreover, software is playing an increasing if not dominant role especially in this platform derivative game, resulting in a burning need for a software and hardware functional co-verification solution at the integrated SOC level but also in the early Intellectual Property (IP) development cycles.