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Reliability Implications of Bias-Temperature Instability in Digital ICs
November/December 2009 (vol. 26 no. 6)
pp. 8-17
Editor's note:
Bias temperature instability (BTI) is one of the major reliability challenges in nanoscale CMOS technology. This article investigates the severity of such degradation in logic and memory circuits. The simulation results reveal that BTI poses severe constraints on reliable memory design, especially in the presence of random process variations.
—Yu Cao, Arizona State University
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Index Terms:
design and test, bias-temperature instability, NBTI, random logic, memory array, random process variation, RDF, PTM, nanoscale technology, Si-H bonds
Citation:
Sang Phill Park, Kunhyuk Kang, Kaushik Roy, "Reliability Implications of Bias-Temperature Instability in Digital ICs," IEEE Design and Test of Computers, vol. 26, no. 6, pp. 8-17, Nov./Dec. 2009, doi:10.1109/MDT.2009.154
