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Accelerating Emulation and Providing Full Chip Observability and Controllability
November/December 2009 (vol. 26 no. 6)
pp. 84-94
ASCII Text
x 
 
Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, "Accelerating Emulation and Providing Full Chip Observability and Controllability," IEEE Design and Test of Computers, vol. 26, no. 6, pp. 84-94, November/December, 2009.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2009.136,
author = {Iakovos Mavroidis and Ioannis Mavroidis and Ioannis Papaefstathiou},
title = {Accelerating Emulation and Providing Full Chip Observability and Controllability},
journal ={IEEE Design and Test of Computers},
volume = {26},
number = {6},
issn = {0740-7475},
year = {2009},
pages = {84-94},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.136},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Accelerating Emulation and Providing Full Chip Observability and Controllability
IS - 6
SN - 0740-7475
SP84
EP94
EPD - 84-94
A1 - Iakovos Mavroidis,
A1 - Ioannis Mavroidis,
A1 - Ioannis Papaefstathiou,
PY - 2009
KW - accelerator
KW - controllability
KW - design and test
KW - embedded logic analyzer
KW - emulator
KW - FPGA
KW - hardware simulation
KW - observability
KW - verification
VL - 26
JA - IEEE Design and Test of Computers
ER -
 
Iakovos Mavroidis, Technical University of Crete
Ioannis Mavroidis, Technical University of Crete
Ioannis Papaefstathiou, Technical University of Crete

The authors deploy an emulation framework that automatically transforms certain Hardware Description Language (HDL) parts of the testbench into synthesizable code to offload the software simulator and minimize the communication overhead. They also extend this architecture by adding multiple fast scan-chain paths in the design to provide full circuit observability and controllability on the fly.

1. I. Mavroidis and I. Papaefstathiou, "Efficient Testbench Code Synthesis for a Hardware Emulator System," Proc. Design, Automation, and Test in Europe (DATE 07), ACM Press, 2007, pp. 888-893.
2. I. Mavroidis and I. Papaefstathiou, "Accelerating Hardware Simulation: Testbench Code Emulation," Proc. IEEE Conf. Field Programmable Technology (ICFPT 08), IEEE Press, 2008, pp. 129-136.
3. M.J.S. Smith, Application Specific Integrated Circuits, Addison-Wesley, 1997, p. 764.
4. T. Wheeler et al., "Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification," Proc. 11th Int'l Conf. Field-Programmable Logic and Applications, IEEE Press, 2001, pp. 483-492.

Index Terms:
accelerator, controllability, design and test, embedded logic analyzer, emulator, FPGA, hardware simulation, observability, verification
Citation:
Iakovos Mavroidis, Ioannis Mavroidis, Ioannis Papaefstathiou, "Accelerating Emulation and Providing Full Chip Observability and Controllability," IEEE Design and Test of Computers, vol. 26, no. 6, pp. 84-94, Nov./Dec. 2009, doi:10.1109/MDT.2009.136
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