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A Novel Simulation Fault Injection Method for Dependability Analysis
November/December 2009 (vol. 26 no. 6)
pp. 50-61
Editor's note:
Presilicon testing and verification is a crucial step in qualifying the RTL for the subsequent implementation phases. This article presents a novel simulation-based fault injection methodology that is applied at the system description level, as opposed to the lower, flattened RT level, in order to reduce simulation time.
—Pradip Bose, IBM Research
1. C.E. Stroud, "Reliability of Majority Voting Based VLSI Fault-Tolerant Circuits," IEEE Trans. Very Large Scale Integration Systems, vol. 2, no. 4, 1994, pp. 516-521.
2. I. Koren and C.M. Krishna, Fault-Tolerant Systems, Morgan Kaufmann, 2007.
3. IEEE Std. 1633, IEEE Recommended Practice on Software Reliability, IEEE, 2008.
4. J. Arlat et al., "Fault Injection for Dependability Validation—A Methodology and Some Applications," IEEE Trans. Software Eng., vol. 16, no. 2, 1990, pp. 166-182.
5. D. Gil et al., "VHDL Simulation-Based Fault Injection Techniques," Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, A. Benso, and P. Prinetto eds., Kluwer Academic Publishers, 2003, pp. 159-176.
6. A. Benso, and P. Prinetto, eds., Fault Injection Techniques and Tools for Embedded Systems Reliability Evaluation, Kluwer Academic Publishers, 2003.
7. V. Krishnaswamy, J. Casas, and T. Tetzlaff, "A Switch Level Fault Simulation Environment," Proc. 37th Ann. Design Automation Conf. (DAC 00), ACM Press, 2000, pp. 780-785.
8. S.Z. Shazli and M.B. Tahoori, "Obtaining Microprocessor Vulnerability Factor Using Formal Methods," IEEE Int'l Symp. Defect and Fault Tolerance of VLSI Systems, IEEE Press, 2008, pp. 63-71.
9. D.A. Patterson and J.L. Hennessy, Computer Organization and Design: The Hardware/Software Interface, Morgan Kaufmann, 2005.
10. S. Mukherjee, Architecture Design for Soft Errors, Morgan Kaufmann, 2007, pp. 149-150, 154.
11. B.W. Johnson, Design and Analysis of Fault Tolerant Digital Systems, Addison-Wesley, 1989, pp. 169-175.
12. J. Yoo, "Harnessing Checker Hierarchy for Reliable Microprocessors," doctoral dissertation, ECE Dept., Univ. of Maryland, 2007, pp. 84-88.
Index Terms:
design and test, electronic systems level, fault injection, kernel-based fault injection, reliability
Citation:
Dongwoo Lee, Jongwhoa Na, "A Novel Simulation Fault Injection Method for Dependability Analysis," IEEE Design and Test of Computers, vol. 26, no. 6, pp. 50-61, Nov./Dec. 2009, doi:10.1109/MDT.2009.135
