Backend geometries on chips contain a wide variety of features. This paper analyzes data from test structures implemented on a 45nm technology test chip to relate geometry to failure rate statistics for low-k dielectric breakdown. An area scaling model is constructed which accounts for the presence of die-to-die linewidth variation, and a methodology is proposed to determine if low-k materials satisfy lifetime requirements in the presence of die-to-die linewidth variation.
Index Terms:
yield, semiconductor test, B.1.3 Control Structure Reliability, Testing, and Fault-Tolerance, B.5 Register-Transfer-Level Implementation, B.2.2 Performance Analysis and Design Aids, B.2.3 Reliability, Testing, and Fault-Tolerance, B.8.1 Reliability, Testing, and Fault-Tolerance, J.6.b Computer-aided manufacturing, B.6.2 Reliability and Testing,
Citation:
Linda Milor, "Modeling Low-K Dielectric Breakdown in the Presence of Multiple Feature Geometries and Die-to-Die Linewidth Variation," IEEE Design and Test of Computers, 26 Oct. 2009. IEEE computer Society Digital Library. IEEE Computer Society, <http://doi.ieeecomputersociety.org/10.1109/MDT.2009.131>
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