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Statistics in Semiconductor Test: Going beyond Yield
September/October 2009 (vol. 26 no. 5)
pp. 64-73
ASCII Text
x 
 
W. Robert Daasch, C. Glenn Shirley, Amit Nahar, "Statistics in Semiconductor Test: Going beyond Yield," IEEE Design and Test of Computers, vol. 26, no. 5, pp. 64-73, September/October, 2009.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2009.123,
author = {W. Robert Daasch and C. Glenn Shirley and Amit Nahar},
title = {Statistics in Semiconductor Test: Going beyond Yield},
journal ={IEEE Design and Test of Computers},
volume = {26},
number = {5},
issn = {0740-7475},
year = {2009},
pages = {64-73},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2009.123},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Statistics in Semiconductor Test: Going beyond Yield
IS - 5
SN - 0740-7475
SP64
EP73
EPD - 64-73
A1 - W. Robert Daasch,
A1 - C. Glenn Shirley,
A1 - Amit Nahar,
PY - 2009
KW - statistical test
KW - design and test
KW - statistical modeling
KW - multisite testing
KW - burn-in
KW - outlier identification
KW - outlier screening
KW - data mining
VL - 26
JA - IEEE Design and Test of Computers
ER -
 
W. Robert Daasch, Portland State University
C. Glenn Shirley, Portland State University
Amit Nahar, Texas Instruments

Editor's note:

The quantity and complexity of data generated at each test manufacturing step can be daunting. This article, which emerged from a tutorial presented at ITC 2008, explains the application of statistics to help process that data and provides examples of how test has shifted from descriptive to predictive methods.

—Nur A. Touba, University of Texas

1. K. Butler et al., "Multi-dimensional Test Escape Rate Modeling," IEEE Design and Test, vol. 26, no. 5, 2009, pp. 74-82.
2. R.V. Hogg, A. Craig, and J.W. McKean, Introduction to Mathematical Statistics, 6th ed., Prentice Hall, 2005.
3. T. Hastie, R. Tibshriani, and J. Friedman, Elements of Statistical Learning: Data Mining, Inference, Prediction, 2nd ed., Springer, 2009.
4. N. Velamatti and W.R. Daasch, "Analytical Model for Multi-site Efficiency with Parallel to Serial Test Times, Yield and Clustering," Proc. 27th IEEE VLSI Test Symp. (VTS 09), IEEE CS Press, 2009, pp. 270-275.
5. C.H. Stapper, "Modeling of Integrated Circuit Defect Sensitivities," IBM J. Research and Development, Nov. 1983, pp. 549-557.
6. W.R. Daasch et al., "Neighborhood Selection for IDDQOutlier Screening," IEEE Design and Test, vol. 19, no. 5, 2002, pp. 74-81.
7. S. Sabade and D. Walker, "Use of Multiple IDDQ Test Metrics for Outlier Identification," Proc. 22nd IEEE VLSI Test Symp. (VTS 03), IEEE CS Press, 2003, pp. 31-38.
8. A. Nahar, R. Daasch, and S. Subramaniam, "Burn-in Reduction Using Principal Component Analysis," Proc. IEEE Int'l Test Conf. (ITC 05), IEEE CS Press, 2005, pp. 155-164.

Index Terms:
statistical test, design and test, statistical modeling, multisite testing, burn-in, outlier identification, outlier screening, data mining
Citation:
W. Robert Daasch, C. Glenn Shirley, Amit Nahar, "Statistics in Semiconductor Test: Going beyond Yield," IEEE Design and Test of Computers, vol. 26, no. 5, pp. 64-73, Sep./Oct. 2009, doi:10.1109/MDT.2009.123
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