Simultaneous Switching Noise: The Relation between Bus Layout and Coding

Design&Test
2008
Issue No. 1 - January-February
Abstract - Simultaneous Switching Noise: The Relation between Bus Layout and Coding

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January-February 2008 (vol. 25 no. 1)

pp. 76-86

	ASCII Text	x
	Daniele Rossi, André K. Nieuwland, Cecilia Metra, "Simultaneous Switching Noise: The Relation between Bus Layout and Coding," IEEE Design and Test of Computers, vol. 25, no. 1, pp. 76-86, January-February, 2008.

	BibTex	x
	@article{ 10.1109/MDT.2008.25, author = {Daniele Rossi and André K. Nieuwland and Cecilia Metra}, title = {Simultaneous Switching Noise: The Relation between Bus Layout and Coding}, journal ={IEEE Design and Test of Computers}, volume = {25}, number = {1}, issn = {0740-7475}, year = {2008}, pages = {76-86}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2008.25}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Simultaneous Switching Noise: The Relation between Bus Layout and Coding IS - 1 SN - 0740-7475 SP76 EP86 EPD - 76-86 A1 - Daniele Rossi, A1 - André K. Nieuwland, A1 - Cecilia Metra, PY - 2008 KW - simultaneous switching noise KW - bus layout KW - coding techniques KW - IC KW - system reliability KW - switching patterns KW - power supply network VL - 25 JA - IEEE Design and Test of Computers ER -

Daniele Rossi, University of Bologna

André K. Nieuwland, NXP Semiconductors

Cecilia Metra, University of Bologna

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2008.25

As device geometries shrink and power supply voltages decrease, simultaneous switching noise (SSN) is having a detrimental effect on IC reliability. This article analyzes the impact of different bus transitions on SSN. Transitions involving the same number of switching signals, but with different placement of switching wires (different switching patterns) within the bus, can induce considerably different levels of SSN. The authors evaluate how SSN varies as a function of the number of switching wires, for different values of wire capacitances. They find that a piecewise linear dependency exists between the SSN and the number of switching wires when the coupling capacitance between adjacent wires is taken into account. Additionally, they analyze the impact of the switching patterns on the effectiveness of the coding techniques that are often proposed to reduce the amount of switching wires and hence SSN. They show that switching-pattern and layout considerations have a significant impact on coding performance. The authors perform their analysis considering realistic bus and power supply network models, both implemented using standard 0.13-micron CMOS technology.

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Index Terms:

simultaneous switching noise, bus layout, coding techniques, IC, system reliability, switching patterns, power supply network

Citation:

Daniele Rossi, André K. Nieuwland, Cecilia Metra, "Simultaneous Switching Noise: The Relation between Bus Layout and Coding," IEEE Design and Test of Computers, vol. 25, no. 1, pp. 76-86, Jan. 2008, doi:10.1109/MDT.2008.25

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