System-in-Package Testing: Problems and Solutions

	This Article
	Subscribers, please Login Purchase article: $19 PDF HTML IEEE Xplore Subscribers RSS feed
	Share
	Email this Article to a friend
	Bibliographic References
	ASCII Text BibTex RefWorks Procite/RefMan/Endnote
	Add to:
	Digg Furl Spurl Blink Simpy Google Del.icio.us Y!MyWeb
	Search
	Similar Articles Articles by Davide Appello Articles by Paolo Bernardi Articles by Michelangelo Grosso Articles by Matteo Sonza Reorda

May/June 2006 (vol. 23 no. 3)

pp. 203-211

	ASCII Text	x
	Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, "System-in-Package Testing: Problems and Solutions," IEEE Design and Test of Computers, vol. 23, no. 3, pp. 203-211, May/June, 2006.

	BibTex	x
	@article{ 10.1109/MDT.2006.79, author = {Davide Appello and Paolo Bernardi and Michelangelo Grosso and Matteo Sonza Reorda}, title = {System-in-Package Testing: Problems and Solutions}, journal ={IEEE Design and Test of Computers}, volume = {23}, number = {3}, issn = {0740-7475}, year = {2006}, pages = {203-211}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2006.79}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - System-in-Package Testing: Problems and Solutions IS - 3 SN - 0740-7475 SP203 EP211 EPD - 203-211 A1 - Davide Appello, A1 - Paolo Bernardi, A1 - Michelangelo Grosso, A1 - Matteo Sonza Reorda, PY - 2006 KW - System-on-Chip KW - System-on-Package KW - System-in-Package KW - SiP KW - SoC KW - test access mechanism KW - IEEE1500 SECT KW - KGD VL - 23 JA - IEEE Design and Test of Computers ER -

Davide Appello, STMicroelectronics

Paolo Bernardi, Politecnico di Torino

Michelangelo Grosso, Politecnico di Torino

Matteo Sonza Reorda, Politecnico di Torino

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2006.79

Editor's note: System-in-package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system-on-chip, which integrates multiple vendor parts. This article provides test strategies for known-good-die and known-good-substrate in the SiP. Case studies provefeasibility using the IEEE 1500 test structure.

Index Terms:

System-on-Chip, System-on-Package, System-in-Package, SiP, SoC, test access mechanism, IEEE1500 SECT, KGD

Citation:

Davide Appello, Paolo Bernardi, Michelangelo Grosso, Matteo Sonza Reorda, "System-in-Package Testing: Problems and Solutions," IEEE Design and Test of Computers, vol. 23, no. 3, pp. 203-211, May/June 2006, doi:10.1109/MDT.2006.79

Peer Review Notice | Give Us Feedback

Usage of this product signifies your acceptance of the Terms of Use.