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Chip-Package Codesign Flow for Mixed-Signal SiP Designs
May/June 2006 (vol. 23 no. 3)
pp. 196-202
ASCII Text
x 
 
Thomas Brandtner, "Chip-Package Codesign Flow for Mixed-Signal SiP Designs," IEEE Design and Test of Computers, vol. 23, no. 3, pp. 196-202, May/June, 2006.
 
 
BibTex
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@article{ 10.1109/MDT.2006.65,
author = {Thomas Brandtner},
title = {Chip-Package Codesign Flow for Mixed-Signal SiP Designs},
journal ={IEEE Design and Test of Computers},
volume = {23},
number = {3},
issn = {0740-7475},
year = {2006},
pages = {196-202},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2006.65},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Chip-Package Codesign Flow for Mixed-Signal SiP Designs
IS - 3
SN - 0740-7475
SP196
EP202
EPD - 196-202
A1 - Thomas Brandtner,
PY - 2006
KW - Mixed-Signal System-in-Package design
KW - SiP
VL - 23
JA - IEEE Design and Test of Computers
ER -
 
Thomas Brandtner, Infineon Technologies
Editor's note: Design engineers are challenged with two separate entities: the chip and package designs. Because system in package integrates multiple dies into a package, design engineers should have a tool to easily combine the two entities. This article demonstrates a seven-die SiP design that implements a chip-and-package codesign platform using available EDA tools.
Index Terms:
Mixed-Signal System-in-Package design, SiP
Citation:
Thomas Brandtner, "Chip-Package Codesign Flow for Mixed-Signal SiP Designs," IEEE Design and Test of Computers, vol. 23, no. 3, pp. 196-202, May/June 2006, doi:10.1109/MDT.2006.65
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