A review of the book, "Verification Methodology Manual for SystemVerilog," by Janick Bergeron et al.
Index Terms:
verification, formal verification, SystemVerilog, design reuse, testbench
Citation:
Brian Bailey, "Was it worth the wait? Yes!," IEEE Design and Test of Computers, vol. 23, no. 2, pp. 160-161, Mar./Apr. 2006, doi:10.1109/MDT.2006.56