Reducing Burn-in Time through High-Voltage Stress Test and Weibull Statistical Analysis March/April 2006 (vol. 23 no. 2) pp. 88-98
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2006.50
Editor's note: High-voltage stress testing (HVST) is common in IC manufacturing, but publications comparing it with other test and burn-in methods are scarce. This article shows that the use of HVST can dramatically reduce the amount of required burn-in. --Phil Nigh, IBM Microelectronics
Index Terms:
integral circuit testing, burn-in reduction, voltage stress, Weibull analysis
Citation:
Mohd Fairuz Zakaria, Zainal Abu Kassim, Melanie Po-Leen Ooi, Serge Demidenko, "Reducing Burn-in Time through High-Voltage Stress Test and Weibull Statistical Analysis," IEEE Design and Test of Computers, vol. 23, no. 2, pp. 88-98, Mar./Apr. 2006, doi:10.1109/MDT.2006.50 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||