On-Chip Testing Techniques for RF Wireless Transceivers July/August 2006 (vol. 23 no. 4) pp. 268-277
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2006.100
This article describes a set of on-chip testing techniques and their application to integrated wireless RF transceivers. The objective is to reduce final product cost and accelerate time to market by providing means of testing the entire transceiver system as well as its major building blocks without using off-chip analog or RF instrumentation. On-chip test devices fabricated in a standard CMOS process and experimentally evaluated support the proposed test strategy.
Index Terms:
Wireless Transceivers, Loop-back test, RF test, Built-in test
Citation:
Alberto Valdes-Garcia, Jose Silva-Martinez, Edgar S?nchez-Sinencio, "On-Chip Testing Techniques for RF Wireless Transceivers," IEEE Design and Test of Computers, vol. 23, no. 4, pp. 268-277, July/Aug. 2006, doi:10.1109/MDT.2006.100 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
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