We IC people have been running scared our entire careers. We?ve worried that the next process node, the next tenfold increase in gate and transistor count, will break our tools and create a set of defects that we don?t know how to test. Delay test is finally mainstream, but besides this most designs use plain-vanilla full-scan test. But we have no reason to be scared; that is, until we get to a very different methodology--for example, nanotechnology, biotechnology, or quantum computing, where the right answer only comes out statistically.