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Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits
July/August 2005 (vol. 22 no. 4)
pp. 362-375
Chong Zhao, University of California, San Diego
Sujit Dey, University of California, San Diego
Xiaoliang Bai, Cadence Design Systems
Soft-spot analysis identifies regions in a circuit that are most susceptible to multiple noise sources and their compound effects so that designers can harden those spots for greater robustness. HSpice simulation validates the methodology's quality, and demonstration on a commercial embedded processor shows its scalability.
Index Terms:
B.8.1 Reliability, Testing, and Fault-Tolerance, G.4.g Reliability and robustness, B.7 Integrated Circuits
Citation:
Chong Zhao, Sujit Dey, Xiaoliang Bai, "Soft-Spot Analysis: Targeting Compound Noise Effects in Nanometer Circuits," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 362-375, July/Aug. 2005, doi:10.1109/MDT.2005.95
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