Modeling and Analysis of Parametric Yield under Power and Performance Constraints

Design&Test
2005
Issue No. 4 - July/August
Abstract - Modeling and Analysis of Parametric Yield under Power and Performance Constraints

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July/August 2005 (vol. 22 no. 4)

pp. 376-385

	ASCII Text	x
	Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan, "Modeling and Analysis of Parametric Yield under Power and Performance Constraints," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 376-385, July/August, 2005.

	BibTex	x
	@article{ 10.1109/MDT.2005.89, author = {Rajeev R. Rao and David Blaauw and Dennis Sylvester and Anirudh Devgan}, title = {Modeling and Analysis of Parametric Yield under Power and Performance Constraints}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {4}, issn = {0740-7475}, year = {2005}, pages = {376-385}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.89}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Modeling and Analysis of Parametric Yield under Power and Performance Constraints IS - 4 SN - 0740-7475 SP376 EP385 EPD - 376-385 A1 - Rajeev R. Rao, A1 - David Blaauw, A1 - Dennis Sylvester, A1 - Anirudh Devgan, PY - 2005 KW - Fault-Tolerance KW - G.4.g Reliability and robustness KW - B.7 Integrated Circuits VL - 22 JA - IEEE Design and Test of Computers ER -

Rajeev R. Rao, University of Michigan, Ann Arbor

David Blaauw, University of Michigan, Ann Arbor

Dennis Sylvester, University of Michigan, Ann Arbor

Anirudh Devgan, Magma Design Automation

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.89

Leakage current is a stringent constraint in today's ASIC designs. Effective parametric yield prediction must consider leakage current's dependence on chip frequency. The authors propose an analytical expression that includes both subthreshold and gate leakage currents. This model underlies an integrated approach to accurately estimating yield loss for a design with both frequency and power limits.

Index Terms:

Fault-Tolerance, G.4.g Reliability and robustness, B.7 Integrated Circuits

Citation:

Rajeev R. Rao, David Blaauw, Dennis Sylvester, Anirudh Devgan, "Modeling and Analysis of Parametric Yield under Power and Performance Constraints," IEEE Design and Test of Computers, vol. 22, no. 4, pp. 376-385, July/Aug. 2005, doi:10.1109/MDT.2005.89

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