Yield-Driven, False-Path-Aware Clock Skew Scheduling

Design&Test
2005
Issue No. 3 - May/June
Abstract - Yield-Driven, False-Path-Aware Clock Skew Scheduling

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	Similar Articles Articles by Jeng-Liang Tsai Articles by Dong Hyun Baik Articles by Charlie Chung-Ping Chen Articles by Kewal K. Saluja

May/June 2005 (vol. 22 no. 3)

pp. 214-222

	ASCII Text	x
	Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja, "Yield-Driven, False-Path-Aware Clock Skew Scheduling," IEEE Design and Test of Computers, vol. 22, no. 3, pp. 214-222, May/June, 2005.

	BibTex	x
	@article{ 10.1109/MDT.2005.75, author = {Jeng-Liang Tsai and Dong Hyun Baik and Charlie Chung-Ping Chen and Kewal K. Saluja}, title = {Yield-Driven, False-Path-Aware Clock Skew Scheduling}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {3}, issn = {0740-7475}, year = {2005}, pages = {214-222}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.75}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Yield-Driven, False-Path-Aware Clock Skew Scheduling IS - 3 SN - 0740-7475 SP214 EP222 EPD - 214-222 A1 - Jeng-Liang Tsai, A1 - Dong Hyun Baik, A1 - Charlie Chung-Ping Chen, A1 - Kewal K. Saluja, PY - 2005 KW - clock skew scheduling KW - performance-related circuit yield loss KW - circuit-level parameters KW - DFM VL - 22 JA - IEEE Design and Test of Computers ER -

Jeng-Liang Tsai, University of Wisconsin-Madison

Dong Hyun Baik, University of Wisconsin-Madison

Charlie Chung-Ping Chen, University of Wisconsin-Madison

Kewal K. Saluja, University of Wisconsin-Madison

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.75

This article proposes clock skew scheduling as a tool to address causes of performance-related circuit yield loss. It is an interesting example of how managing circuit-level parameters can have a direct impact on yield metrics and, therefore, a clear example of the direction of DFM research.

Index Terms:

clock skew scheduling, performance-related circuit yield loss, circuit-level parameters, DFM

Citation:

Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Ping Chen, Kewal K. Saluja, "Yield-Driven, False-Path-Aware Clock Skew Scheduling," IEEE Design and Test of Computers, vol. 22, no. 3, pp. 214-222, May/June 2005, doi:10.1109/MDT.2005.75

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