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Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below
May/June 2005 (vol. 22 no. 3)
pp. 232-239
ASCII Text
x 
 
Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green, "Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below," IEEE Design and Test of Computers, vol. 22, no. 3, pp. 232-239, May/June, 2005.
 
 
BibTex
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@article{ 10.1109/MDT.2005.63,
author = {Greg Yeric and Ethan Cohen and John Garcia and Kurt Davis and Esam Salem and Gary Green},
title = {Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below},
journal ={IEEE Design and Test of Computers},
volume = {22},
number = {3},
issn = {0740-7475},
year = {2005},
pages = {232-239},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.63},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below
IS - 3
SN - 0740-7475
SP232
EP239
EPD - 232-239
A1 - Greg Yeric,
A1 - Ethan Cohen,
A1 - John Garcia,
A1 - Kurt Davis,
A1 - Esam Salem,
A1 - Gary Green,
PY - 2005
KW - systematic yield loss
KW - test structure
KW - BEOL
KW - infrastructure IP
KW - process monitoring
KW - silicon debug
KW - DFM
VL - 22
JA - IEEE Design and Test of Computers
ER -
 
Greg Yeric, HPL Technologies
Ethan Cohen, HPL Technologies
John Garcia, HPL Technologies
Kurt Davis, HPL Technologies
Esam Salem, HPL Technologies
Gary Green, HPL Technologies
Optimized test structures are necessary to measure and analyze the causes for systematic yield loss. This article introduces a novel test structure for BEOL—an infrastructure IP for process monitoring. It also describes a method for characterizing and measuring yield ramp issues and solutions for improving silicon debug and DFM.
Index Terms:
systematic yield loss, test structure, BEOL, infrastructure IP, process monitoring, silicon debug , DFM
Citation:
Greg Yeric, Ethan Cohen, John Garcia, Kurt Davis, Esam Salem, Gary Green, "Infrastructure for Successful BEOL Yield Ramp, Transfer to Manufacturing, and DFM Characterization at 65 nm and Below," IEEE Design and Test of Computers, vol. 22, no. 3, pp. 232-239, May/June 2005, doi:10.1109/MDT.2005.63
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