Predicting the Performance of a 3D Processor-Memory Chip Stack

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	Similar Articles Articles by Philip Jacob Articles by Okan Erdogan Articles by Aamir Zia Articles by Paul M. Belemjian Articles by Russell P. Kraft Articles by John F. McDonald

November/December 2005 (vol. 22 no. 6)

pp. 540-547

	ASCII Text	x
	Philip Jacob, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald, "Predicting the Performance of a 3D Processor-Memory Chip Stack," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 540-547, November/December, 2005.

	BibTex	x
	@article{ 10.1109/MDT.2005.151, author = {Philip Jacob and Okan Erdogan and Aamir Zia and Paul M. Belemjian and Russell P. Kraft and John F. McDonald}, title = {Predicting the Performance of a 3D Processor-Memory Chip Stack}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {6}, issn = {0740-7475}, year = {2005}, pages = {540-547}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.151}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Predicting the Performance of a 3D Processor-Memory Chip Stack IS - 6 SN - 0740-7475 SP540 EP547 EPD - 540-547 A1 - Philip Jacob, A1 - Okan Erdogan, A1 - Aamir Zia, A1 - Paul M. Belemjian, A1 - Russell P. Kraft, A1 - John F. McDonald, PY - 2005 KW - Cache memories KW - Simulation KW - Performance of Systems VL - 22 JA - IEEE Design and Test of Computers ER -

Philip Jacob, Rensselaer Polytechnic Institute

Okan Erdogan, Rensselaer Polytechnic Institute

Aamir Zia, Rensselaer Polytechnic Institute

Paul M. Belemjian, Rensselaer Polytechnic Institute

Russell P. Kraft, Rensselaer Polytechnic Institute

John F. McDonald, Rensselaer Polytechnic Institute

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.151

A primary bottleneck in the performance of a processor is in its communication with memory. By allowing the placement of processor and memory in adjacent layers, 3D design provides significant relief, reducing the communication latency. This article studies the impact of 3D design bycomparing the cycles per instruction of such a design with various alternatives.

Index Terms:

Cache memories, Simulation, Performance of Systems

Citation:

Philip Jacob, Okan Erdogan, Aamir Zia, Paul M. Belemjian, Russell P. Kraft, John F. McDonald, "Predicting the Performance of a 3D Processor-Memory Chip Stack," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 540-547, Nov./Dec. 2005, doi:10.1109/MDT.2005.151

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