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IC Outlier Identification Using Multiple Test Metrics
November/December 2005 (vol. 22 no. 6)
pp. 586-595
ASCII Text
x 
 
Sagar S. Sabade, Duncan M. Walker, "IC Outlier Identification Using Multiple Test Metrics," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 586-595, November/December, 2005.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2005.143,
author = {Sagar S. Sabade and Duncan M. Walker},
title = {IC Outlier Identification Using Multiple Test Metrics},
journal ={IEEE Design and Test of Computers},
volume = {22},
number = {6},
issn = {0740-7475},
year = {2005},
pages = {586-595},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.143},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - IC Outlier Identification Using Multiple Test Metrics
IS - 6
SN - 0740-7475
SP586
EP595
EPD - 586-595
A1 - Sagar S. Sabade,
A1 - Duncan M. Walker,
PY - 2005
KW - Control Structure Reliability
KW - Testing
KW - and Fault-Tolerance
KW - Reliability and Testing
VL - 22
JA - IEEE Design and Test of Computers
ER -
 
Sagar S. Sabade, Texas Instruments
Duncan M. Walker, Texas A&M University
The use of IDDQ as a test method has been threatened by high leakage currents in nanometer designs. This article suggests a method for keeping it useful and also delineates some of the challenges in recognizing and rejecting outlier parts.
Index Terms:
Control Structure Reliability, Testing, and Fault-Tolerance, Reliability and Testing
Citation:
Sagar S. Sabade, Duncan M. Walker, "IC Outlier Identification Using Multiple Test Metrics," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 586-595, Nov./Dec. 2005, doi:10.1109/MDT.2005.143
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