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First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration
November/December 2005 (vol. 22 no. 6)
pp. 548-555
ASCII Text
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Annie (Yujuan) Zeng, James (JianQiang) L?, Kenneth Rose, Ronald J. Gutmann, "First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 548-555, November/December, 2005.
 
 
BibTex
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@article{ 10.1109/MDT.2005.138,
author = {Annie (Yujuan) Zeng and James (JianQiang) L? and Kenneth Rose and Ronald J. Gutmann},
title = {First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration},
journal ={IEEE Design and Test of Computers},
volume = {22},
number = {6},
issn = {0740-7475},
year = {2005},
pages = {548-555},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.138},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration
IS - 6
SN - 0740-7475
SP548
EP555
EPD - 548-555
A1 - Annie (Yujuan) Zeng,
A1 - James (JianQiang) L?,
A1 - Kenneth Rose,
A1 - Ronald J. Gutmann,
PY - 2005
KW - Access time
KW - cycle time
KW - cache performance
KW - wafer-level 3D integration
KW - SRAM
KW - DRAM
VL - 22
JA - IEEE Design and Test of Computers
ER -
 
Annie (Yujuan) Zeng, Rensselaer Polytechnic Institute
James (JianQiang) L?, Rensselaer Polytechnic Institute
Kenneth Rose, Rensselaer Polytechnic Institute
Ronald J. Gutmann, Rensselaer Polytechnic Institute
The advantages of 3D design can be exploited by reducing the memoryaccess time. In this article, the authors use a simulator based on analyticalmodels to build an optimal processor-memory configuration for two designs:a graphics processor and a microprocessor.
Index Terms:
Access time, cycle time, cache performance, wafer-level 3D integration, SRAM, DRAM
Citation:
Annie (Yujuan) Zeng, James (JianQiang) L?, Kenneth Rose, Ronald J. Gutmann, "First-Order Performance Prediction of Cache Memory with Wafer-Level3D Integration," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 548-555, Nov./Dec. 2005, doi:10.1109/MDT.2005.138
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