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3D Chip Stack Technology Using Through-Chip Interconnects
November/December 2005 (vol. 22 no. 6)
pp. 512-518
ASCII Text
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Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Joerg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher, "3D Chip Stack Technology Using Through-Chip Interconnects," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 512-518, November/December, 2005.
 
 
BibTex
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@article{ 10.1109/MDT.2005.125,
author = {Peter Benkart and Alexander Kaiser and Andreas Munding and Markus Bschorr and Hans-Joerg Pfleiderer and Erhard Kohn and Arne Heittmann and Holger Huebner and Ulrich Ramacher},
title = {3D Chip Stack Technology Using Through-Chip Interconnects},
journal ={IEEE Design and Test of Computers},
volume = {22},
number = {6},
issn = {0740-7475},
year = {2005},
pages = {512-518},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.125},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - 3D Chip Stack Technology Using Through-Chip Interconnects
IS - 6
SN - 0740-7475
SP512
EP518
EPD - 512-518
A1 - Peter Benkart,
A1 - Alexander Kaiser,
A1 - Andreas Munding,
A1 - Markus Bschorr,
A1 - Hans-Joerg Pfleiderer,
A1 - Erhard Kohn,
A1 - Arne Heittmann,
A1 - Holger Huebner,
A1 - Ulrich Ramacher,
PY - 2005
KW - General
KW - Integrated Circuits General
VL - 22
JA - IEEE Design and Test of Computers
ER -
 
Peter Benkart, Infineon Technologies and University of Ulm
Alexander Kaiser, University of Ulm
Andreas Munding, University of Ulm
Markus Bschorr, University of Ulm
Hans-Joerg Pfleiderer, University of Ulm
Erhard Kohn, University of Ulm
Arne Heittmann, Infineon Technologies
Holger Huebner, Infineon Technologies
Ulrich Ramacher, Infineon Technologies
A key enabler for 3D technologies is the ability to stack chips and buildinterconnects that connect circuitry in different layers of the stack. This articlepresents a technology overview of how to achieve this goal in a 3D fabricationprocess. It also shows measurements for characterizing these interconnects.
Index Terms:
General, Integrated Circuits General
Citation:
Peter Benkart, Alexander Kaiser, Andreas Munding, Markus Bschorr, Hans-Joerg Pfleiderer, Erhard Kohn, Arne Heittmann, Holger Huebner, Ulrich Ramacher, "3D Chip Stack Technology Using Through-Chip Interconnects," IEEE Design and Test of Computers, vol. 22, no. 6, pp. 512-518, Nov./Dec. 2005, doi:10.1109/MDT.2005.125
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