Analysis of Error Recovery Schemes for Networks on Chips

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	Similar Articles Articles by Srinivasan Murali Articles by Theocharis Theocharides Articles by N. Vijaykrishnan Articles by Mary Jane Irwin Articles by Luca Benini Articles by Giovanni De Micheli

September/October 2005 (vol. 22 no. 5)

pp. 434-442

	ASCII Text	x
	Srinivasan Murali, Theocharis Theocharides, N. Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli, "Analysis of Error Recovery Schemes for Networks on Chips," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 434-442, September/October, 2005.

	BibTex	x
	@article{ 10.1109/MDT.2005.104, author = {Srinivasan Murali and Theocharis Theocharides and N. Vijaykrishnan and Mary Jane Irwin and Luca Benini and Giovanni De Micheli}, title = {Analysis of Error Recovery Schemes for Networks on Chips}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {5}, issn = {0740-7475}, year = {2005}, pages = {434-442}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.104}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Analysis of Error Recovery Schemes for Networks on Chips IS - 5 SN - 0740-7475 SP434 EP442 EPD - 434-442 A1 - Srinivasan Murali, A1 - Theocharis Theocharides, A1 - N. Vijaykrishnan, A1 - Mary Jane Irwin, A1 - Luca Benini, A1 - Giovanni De Micheli, PY - 2005 KW - Performance and Reliability KW - I/O and Data Communications VL - 22 JA - IEEE Design and Test of Computers ER -

Srinivasan Murali, Stanford University

Theocharis Theocharides, Pennsylvania State University

N. Vijaykrishnan, Pennsylvania State University

Mary Jane Irwin, Pennsylvania State University

Luca Benini, University of Bologna

Giovanni De Micheli, Ecole Polytechnique Federale de Lausanne

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.104

Error resiliency is a must for NoCs, but it must not incur undue costs--particularly in terms of energy consumption. Here, the authors present anauthoritative discussion of the trade-offs involved in various error recoveryschemes, enabling designers to make optimal decisions.

Index Terms:

Performance and Reliability, I/O and Data Communications

Citation:

Srinivasan Murali, Theocharis Theocharides, N. Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli, "Analysis of Error Recovery Schemes for Networks on Chips," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 434-442, Sep./Oct. 2005, doi:10.1109/MDT.2005.104

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