Analysis of Error Recovery Schemes for Networks on Chips September/October 2005 (vol. 22 no. 5) pp. 434-442
DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.104
Error resiliency is a must for NoCs, but it must not incur undue costs--particularly in terms of energy consumption. Here, the authors present anauthoritative discussion of the trade-offs involved in various error recoveryschemes, enabling designers to make optimal decisions.
Index Terms:
Performance and Reliability, I/O and Data Communications
Citation:
Srinivasan Murali, Theocharis Theocharides, N. Vijaykrishnan, Mary Jane Irwin, Luca Benini, Giovanni De Micheli, "Analysis of Error Recovery Schemes for Networks on Chips," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 434-442, Sep./Oct. 2005, doi:10.1109/MDT.2005.104 Usage of this product signifies your acceptance of the Terms of Use. | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||