Analysis and Implementation of Practical, Cost-Effective Networks on Chips

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September/October 2005 (vol. 22 no. 5)

pp. 422-433

	ASCII Text	x
	Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo, "Analysis and Implementation of Practical, Cost-Effective Networks on Chips," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 422-433, September/October, 2005.

	BibTex	x
	@article{ 10.1109/MDT.2005.103, author = {Se-Joong Lee and Kangmin Lee and Hoi-Jun Yoo}, title = {Analysis and Implementation of Practical, Cost-Effective Networks on Chips}, journal ={IEEE Design and Test of Computers}, volume = {22}, number = {5}, issn = {0740-7475}, year = {2005}, pages = {422-433}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2005.103}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Analysis and Implementation of Practical, Cost-Effective Networks on Chips IS - 5 SN - 0740-7475 SP422 EP433 EPD - 422-433 A1 - Se-Joong Lee, A1 - Kangmin Lee, A1 - Hoi-Jun Yoo, PY - 2005 KW - Advanced technologies KW - Network connectivity chips KW - VLSI VL - 22 JA - IEEE Design and Test of Computers ER -

Se-Joong Lee, Korea Advanced Institute of Science and Technology

Kangmin Lee, Korea Advanced Institute of Science and Technology

Hoi-Jun Yoo, Korea Advanced Institute of Science and Technology

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2005.103

This article describes design issues in three chips that exploit star and meshnetworks, with the objective of comparing area and energy costs. The authorspresent new solutions based on mesochronous communication and burstpacket transactions.

Index Terms:

Advanced technologies, Network connectivity chips, VLSI

Citation:

Se-Joong Lee, Kangmin Lee, Hoi-Jun Yoo, "Analysis and Implementation of Practical, Cost-Effective Networks on Chips," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 422-433, Sep./Oct. 2005, doi:10.1109/MDT.2005.103

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