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Linking Simulation with Formal Verification at a Higher Level
November/December 2004 (vol. 21 no. 6)
pp. 472-482
ASCII Text
x 
 
Serdar Tasiran, Yuan Yu, Brannon Batson, "Linking Simulation with Formal Verification at a Higher Level," IEEE Design and Test of Computers, vol. 21, no. 6, pp. 472-482, November/December, 2004.
 
 
BibTex
x
 
@article{ 10.1109/MDT.2004.94,
author = {Serdar Tasiran and Yuan Yu and Brannon Batson},
title = {Linking Simulation with Formal Verification at a Higher Level},
journal ={IEEE Design and Test of Computers},
volume = {21},
number = {6},
issn = {0740-7475},
year = {2004},
pages = {472-482},
doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.94},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - MGZN
JO - IEEE Design and Test of Computers
TI - Linking Simulation with Formal Verification at a Higher Level
IS - 6
SN - 0740-7475
SP472
EP482
EPD - 472-482
A1 - Serdar Tasiran,
A1 - Yuan Yu,
A1 - Brannon Batson,
PY - 2004
VL - 21
JA - IEEE Design and Test of Computers
ER -
 
Serdar Tasiran, Ko? University
Yuan Yu, Microsoft Research
Editor's note: This article uses simulation to bridge the gap between specification and formal verification of high-level models and simulation of RTL models. The authors apply their practical, two-phase procedure for defining the refinement map to the Alpha 21364 multiprocessing hardware. The methodology and tools they present can improve simulation coverage. —Carl Pixley, Synopsys
Citation:
Serdar Tasiran, Yuan Yu, Brannon Batson, "Linking Simulation with Formal Verification at a Higher Level," IEEE Design and Test of Computers, vol. 21, no. 6, pp. 472-482, Nov./Dec. 2004, doi:10.1109/MDT.2004.94
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