Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation

Design&Test
2004
Issue No. 6 - November/December
Abstract - Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation

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November/December 2004 (vol. 21 no. 6)

pp. 494-502

	ASCII Text	x
	Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir, "Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation," IEEE Design and Test of Computers, vol. 21, no. 6, pp. 494-502, November/December, 2004.

	BibTex	x
	@article{ 10.1109/MDT.2004.87, author = {Jayanta Bhadra and Narayanan Krishnamurthy and Magdy S. Abadir}, title = {Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation}, journal ={IEEE Design and Test of Computers}, volume = {21}, number = {6}, issn = {0740-7475}, year = {2004}, pages = {494-502}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.87}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation IS - 6 SN - 0740-7475 SP494 EP502 EPD - 494-502 A1 - Jayanta Bhadra, A1 - Narayanan Krishnamurthy, A1 - Magdy S. Abadir, PY - 2004 VL - 21 JA - IEEE Design and Test of Computers ER -

Jayanta Bhadra, Freescale Semiconductor

Narayanan Krishnamurthy, Freescale Semiconductor

Magdy S. Abadir, Freescale Semiconductor

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.87

Editor's note: This article, from the Motorola (now Freescale) PowerPC design group, presents an interesting synergy among test, equivalence verification, and constraints. The authors use RTL, gate, and switch models of a design in two different flows—one for test and one for functional verification—to show that rectifying constraints and merging tests between the two flows saves significant presilicon debug effort.

Citation:

Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir, "Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation," IEEE Design and Test of Computers, vol. 21, no. 6, pp. 494-502, Nov./Dec. 2004, doi:10.1109/MDT.2004.87

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