Defect and Error Tolerance in the Presence of Massive Numbers of Defects

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	Similar Articles Articles by Melvin A. Breuer Articles by Sandeep K. Gupta Articles by T.M. Mak

May/June 2004 (vol. 21 no. 3)

pp. 216-227

	ASCII Text	x
	Melvin A. Breuer, Sandeep K. Gupta, T.M. Mak, "Defect and Error Tolerance in the Presence of Massive Numbers of Defects," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 216-227, May/June, 2004.

	BibTex	x
	@article{ 10.1109/MDT.2004.8, author = {Melvin A. Breuer and Sandeep K. Gupta and T.M. Mak}, title = {Defect and Error Tolerance in the Presence of Massive Numbers of Defects}, journal ={IEEE Design and Test of Computers}, volume = {21}, number = {3}, issn = {0740-7475}, year = {2004}, pages = {216-227}, doi = {http://doi.ieeecomputersociety.org/10.1109/MDT.2004.8}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }

	RefWorks Procite/RefMan/Endnote	x
	TY - MGZN JO - IEEE Design and Test of Computers TI - Defect and Error Tolerance in the Presence of Massive Numbers of Defects IS - 3 SN - 0740-7475 SP216 EP227 EPD - 216-227 A1 - Melvin A. Breuer, A1 - Sandeep K. Gupta, A1 - T.M. Mak, PY - 2004 VL - 21 JA - IEEE Design and Test of Computers ER -

Melvin A. Breuer, University of Southern California

Sandeep K. Gupta, University of Southern California

T.M. Mak, Intel

DOI Bookmark: http://doi.ieeecomputersociety.org/10.1109/MDT.2004.8

As scaling approaches the physical limits of devices, we will continue to see increasing levels of process variations, noise, and defect densities. Many applications today can tolerate certain levels of errors resulting from such factors. This article introduces a new approach for error tolerance resulting in chips containing only errors acceptable for such applications.

Citation:

Melvin A. Breuer, Sandeep K. Gupta, T.M. Mak, "Defect and Error Tolerance in the Presence of Massive Numbers of Defects," IEEE Design and Test of Computers, vol. 21, no. 3, pp. 216-227, May/June 2004, doi:10.1109/MDT.2004.8

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